It’s 2:48 am. I’ve just recently reached the comforts of my apartment after a lengthy work session in the computer lab with Ryan. I try to avoid posting at this hour of the morning, because I tend to be less than coherent, but I think the jubilation of this moment calls for an exception.

We have a semester project in ECE 551: Digital System Design & Synthesis (aka “Verilog”). The project was assigned in the vicinity of a week or two before Spring Break. That is, we have had in the neighborhood of a month or more to work on it. Of course, we didn’t complete any work at all until we were required to implement one subcomponent for a homework assignment a week ago. So we completed that 2 hours before the deadline, and handed it in. No big deal.

Now tomorrow the initial draft of our project report is due. Initial “draft”, as in: feature-complete implementation of all components, including explanations of how they work, timing and space analysis, and testing to demonstrate their correctness. As of 2:15pm today, Ryan and I had completed exactly 1 major subcomponent, for the aforementioned homework assignment. Less than 12 hours later, including a break for Subway, we were done. There will certainly be things that we need to tune up and optimize for the final report, but every major component of our processor is complete, in place, working perfectly, and passing every test case.  All in less than 12 hours, less than a day before it is due.

Who ever said procrastinators never make it anywhere in this world?

…And now I need some sleep. Badly.